Parameter Estimation of a High Frequency Cascode Low Noise Amplifier Model

A Low Noise Amplifier (LNA) is an important building block in the RF receiver chain. Typically the LNA should provide acceptable gain and high linearity while maintaining low noise and power consumption. To optimize these conflicting goals the so-called Cascode topology is widely used in industry. Here the gain cell is comprised of two transistors, one in common-source and the other in common gate configuration. Cascode has a number of competitive advantages over other topologies such as high output impedance that shields the input device from voltage variations at the output, good reverse isolation resulting in improved stability, and acceptable input matching. Moreover, the topology features excellent frequency characteristics. Unfortunately, a Cascode design is expensive to deploy in RF systems and it requires more careful tuning and matching. Since the design relies on many circuit components, optimization methods are generally difficult to implement and often inaccurate in their predictions. To overcome these problems, this thesis proposes a modeling environment within the Advanced Design Systems (ADS) simulator that utilized DC and RF measurements in an effort to characterize each transistor separately. The model creates an easy-to-apply design approach capable of predicting the most important circuit components of the Cascode topology. The validity of the method is tested in ADS with a realistic p-HEMT library device. The comparison between model prediction and the realistic device involves both standard transistor parameters and high-frequency parasitic effects. ii Acknowledgement